Our client has requested @Orchard engage a contractor experienced as an ASIC.FPGA Design Engineer, to work on ASIC and FPGA design projects that enable privacy, trust, and security by default, in networks everywhere. As the Design Engineer, you will join a team that is tasked to drive more integration, lower power, mixed-signal architectures, and next-generation technology to be deployed in space and ground infrastructures. You will focus on digital signal processing (DSP) and digital communication blocks, and enable integration of our ASIC/FPGA products in partner platforms. This is a contract role, with the potential to be considered for a full-time role with the client after a minimum of a six-month contract period through @Orchard. Owing to the nature of the work, and ultimate client, all eligible consultants must be US-Citizens.

As the ASIC/FPGA Design Engineer your responsibilities can include;

  • Participate in all phases of ASIC/FPGA design flow – from concept to mass production.
  • Develop high-level design requirements and block-level micro-architectures, partition design within ASIC/FPGA, create specification documents.
  • Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.).
  • Optimize your designs for the area, speed, and power to meet system requirements; analyze architectural trade-offs.
  • Develop test benches and test cases for block-level functional verification, emphasizing bit-matching and self-checking.
  • Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers.
  • Collaborate with verification engineers to develop UVM-based top-level tests for your blocks.
  • Participate in SoC-level and FPGA top-level integration activities.
  • Prototype designs on FPGA, focusing on closely emulating the final product functionality.
  • Use scripting languages to achieve higher performance and improve productivity through automation.
  • Perform lint checking, CDC checking, logic equivalence checking, and other EDA tool-based checks.
  • Run implementation tools, such as Synopsys Design Compiler, Xilinx Vivado, and others; perform timing closure for your designs.
  • Work with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICs.
  • Identify and validate ASICs and FPGAs in the lab, utilize various lab equipment.
  • Collaborate with software engineers in developing production software for your designs BASIC.

Your background will include:

  • US Citizenship Required.
  • Bachelor’s degree in electrical engineering, computer engineering, or other engineering disciplines.
  • 2+ years of experience in working with ASICs and/or FPGAs (internship and research experience qualifies).
  • 2+ years of experience in SystemVerilog, Verilog, or VHDL RTL design.
  • 2+ years of experience in scripting and programming languages in two or more of the following: MATLAB, Python, C/C++, Perl, Tcl, Make, Bash.